SPI
SPI (Serial Peripheral Interface) was designed by Motorola in the early-to-mid 1980s and remains a de facto standard with no formal governing spec -- clock polarity/phase (CPOL/CPHA) conventions are defined per-vendor in NXP, Microchip, and ST reference manuals. Standard wiring uses 4 lines (MOSI, MISO, SCLK, CS) for full-duplex transfer; clock speed is device-limited, commonly 1-50 MHz, with Quad/Octal-SPI variants exceeding 200 MHz. Each peripheral needs its own chip-select line, versus I2C's 2-wire bus (100 kbit/s-3.4 Mbit/s, up to 127 addresses, NXP UM10204 spec) or UART's 2-wire point-to-point link (device/clock-limited, commonly well under a few Mbit/s in practice, no clock line). SparkFun/OSHWA formally retired "master/slave" for "controller/peripheral" in 2020 docs. SPI drives flash memory, SD cards, ADCs, and displays on nearly every microcontroller (Arduino, STM32, ESP32, Raspberry Pi). Current version/status: Unversioned de facto standard (earliest confirmed references ~1983-1985 by Motorola, well-documented by the 1985 M68HC11); no formal spec revision cycle, still dominant in 2026. Modern variants: Dual/Quad/Octal SPI.. License: None -- open, unpatented de facto standard (no licensing fee, unlike I2C's historical NXP/Philips high-speed-mode license). Maintained by No standards body; originated at Motorola semiconductor division (lineage now split across NXP/onsemi)
Pick SPI when you need raw throughput to a single fast peripheral -- flash chips, SD cards, TFT displays, ADCs -- where its full-duplex 1-50+ MHz link beats I2C's 3.4 Mbit/s ceiling. Skip it for multi-sensor boards with limited GPIO: I2C's 2-wire bus scales to dozens of devices on one pair of pins without burning a chip-select line per part. Skip it entirely for long cable runs or noisy environments -- no clock recovery or error checking means UART or RS-485 survive better over distance. The community's own admitted flaw: no ACK bit, no CRC, no flow control, and CPOL/CPHA mismatches between vendors cause silent wiring bugs that a formal spec would have caught decades ago. Known weakness: No acknowledgment bit, error-checking (CRC), or flow control -- a bad connection fails silently -- and per-device chip-select wiring means pin count grows linearly with peripherals, unlike I2C's 2-wire multi-drop bus.